Vertical transistors are a class of semiconductor devices characterized by a vertical conduction path that extends generally from the top of a device to the bottom. Compared with more traditional transistors, which have horizontal conduction paths, generally vertical channel structures allow for both a high blocking voltage and a high on-state current, making such devices well suited for high-power applications.
One example of a vertical transistor is the vertical junction field-effect transistor (JFET) 10 illustrated in FIG. 1. The vertical JFET 10 is an example of an N-channel depletion mode device, which means that the device is in its on-state when no charge is applied to the gate contacts 12 (G). In its on-state, the gate contacts 12 (G) above the P-doped control regions 14 are under forward bias, and do not deplete the N-doped drift region 16. In this state, current can flow between the source contact 18 (S) and the drain contact 20 (D), across the substrate 22, drift layer 24, and drift region 16. To block this current, a negative bias can be applied to the gate contacts 12 (G), causing depletion of the drift region 16. Thus reducing or eliminating the on-state current and switching the vertical JFET 10 to its off-state. Conventional vertical metal oxide semiconductor field-effect transistors (MOSFETs) are similar to the vertical JFET 10 of FIG. 1; however, the vertical MOSFETs are normally in an off-state.
Gallium nitride (GaN) is a III-V semiconductor material with a wide bandgap, very high breakdown voltages, and high electron mobility, making it an ideal candidate for use in high-power devices such as the vertical JFET 10 illustrated in FIG. 1. However, current fabrication techniques used for vertical GaN devices requiring several regrowth steps are often inefficient or can result in PN junctions having high defect densities at interfaces between P-doped regions and N-doped regions due to the regrowth. Since dislocations typically provide current leakage paths for vertical transistors, bulk GaN substrates with a low number of dislocation densities are conventionally used for fabricating vertical transistors. However, the regrowth of N-doped GaN regions on P-doped GaN surfaces can introduce chemical contaminants and other damage related with the dry etching process and the cleaning process. These chemical contaminants and process related damage can increase impurity backgrounds and create point defects that produce leakage paths at the regrowth surfaces, resulting in devices that suffer from high current leakages and lower breakdown voltages. Therefore, there is a need for an efficient fabrication technique that reduces or eliminates interface defects at PN junctions in vertical transistors, and in particular, GaN-based transistors.